t_a_clk.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_a_clk.vhd
-- Testbench for the complete Alarm Clock design (Lab 13)
--
----------------------------------------------------

Library IEEE;
use IEEE.Std_Logic_1164.all; 
use std.textio.all;

use work.P_ALARM_TEST.all;   -- package holds procedures defining commands

entity T_A_CLK is
end T_A_CLK;

architecture TEST of T_A_CLK is

   signal CLK                             : std_logic := '0';
   signal RESET                           : std_logic := '0';
   signal KEYS                            : T_KEYPAD := '-'; -- initial value of "no key"
   signal KEY_ROWS                        : std_logic_vector(3 downto 0);
   signal KEY_COLUMNS                     : std_logic_vector(2 downto 0);
   signal SOUND_ALARM                     : std_logic;
   signal TIE_LOW                         : std_logic := '0';
   signal DISPLAY_LS_MIN, DISPLAY_MS_MIN, 
          DISPLAY_LS_HR, DISPLAY_MS_HR    : std_logic_vector(6 downto 0);
   -- debug signals
   signal LS_MIN, MS_MIN, LS_HR, MS_HR    : CHARACTER;
   signal SIM_END                         : boolean := FALSE;
   constant PERIOD                        : time := 3.9 ms; -- 256Hz period

component A_CLK
port ( CLK              : in std_logic;
       RESET            : in std_logic;
       STOPWATCH        : in std_logic;
       KEYPAD_ROWS      : in std_logic_vector(3 downto 0);
       KEYPAD_COLUMNS   : out std_logic_vector(2 downto 0);
       SOUND_ALARM      : out std_logic;
       DISPLAY_LS_MIN   : out std_logic_vector(6 downto 0);
       DISPLAY_MS_MIN   : out std_logic_vector(6 downto 0);
       DISPLAY_LS_HR    : out std_logic_vector(6 downto 0);
       DISPLAY_MS_HR    : out std_logic_vector(6 downto 0));
end component;

component KEYPAD
port ( KEY: in T_KEYPAD;
       COLUMNS : in std_logic_vector(2 downto 0);
       ROWS: out std_logic_vector(3 downto 0));
end component;

begin 
   -- Generate CLK and Reset waveforms
   CLK <= not CLK after PERIOD/2 when SIM_END = FALSE else '0'; 
   RESET <= '1' after PERIOD, '0' after 3*PERIOD; 

   -- Instantiate the block under test

   U_ALARM_CLOCK: A_CLK
   port map ( CLK => CLK,
              RESET => RESET,
              STOPWATCH => TIE_LOW,
              KEYPAD_ROWS => KEY_ROWS,
              KEYPAD_COLUMNS => KEY_COLUMNS,
              SOUND_ALARM => SOUND_ALARM,
              DISPLAY_LS_MIN => DISPLAY_LS_MIN,
              DISPLAY_MS_MIN => DISPLAY_MS_MIN,
              DISPLAY_LS_HR => DISPLAY_LS_HR,
              DISPLAY_MS_HR => DISPLAY_MS_HR);

   U_KEYPAD_MODEL: KEYPAD
   port map(KEY => KEYS,
            COLUMNS => KEY_COLUMNS,
            ROWS => KEY_ROWS);

------------------------------------------------------------------------
-- COMMAND INPUT process
-- This process reads command strings from  the test file "command.txt"
-- and generates input stimulus to the block under test, depending upon
-- which command is read in. The commands are:
--
-- SETAL DDDD -- set alarm <time> 
-- SETTI DDDD -- set time  <time>
-- SHWAL      -- show alarm
-- COUNT D    -- advance the clock by D <periods>
-- KTOUT      -- test the keypad timeout
--
-- (D = integer ascii character in range 0-9)
------------------------------------------------------------------------
   COMMAND_INPUT: process 
      file COMFILE                   : text is in "command.txt";
      variable L                     : line;
      variable CMD                   : string(1 to 5);
      variable SETTING               : string(1 to 4);
      variable COUNT_SEC, SEPARATOR     : character;
   begin
      -- if there are still lines to read in the text file ...
      while not ENDFILE(COMFILE) loop

         -- read in next line from text file, then read the first text string
         -- from the line and call this CMD.
         readline(COMFILE, L);
         read (L, CMD);

         -- Depending on what the command is, read in any extra information
         -- from the line read from the file and then "do" the command
         case CMD is
            when "SHALM" => DO_SHALM(KEYS);
            when "SETAL" => read (L, SEPARATOR);
                            read (L, SETTING);
                            DO_SETAL(SETTING, KEYS);
            when "SETTI" => read (L, SEPARATOR);
                            read (L, SETTING);
                            DO_SETTI(SETTING, KEYS);
            when "COUNT" => read(L, SEPARATOR);
                            read(L, COUNT_SEC);
                            DO_COUNT(COUNT_SEC);
            when "KTOUT" => DO_KTOUT(KEYS);
            when others => assert FALSE report "Unrecognised Instruction"
                              severity FAILURE;
         end case;

      end loop;

      -- No new lines to read from file, so report simulation complete and
      -- stop clock generator with SIM_END signal
      assert FALSE report "Simulation complete" severity NOTE;
      SIM_END <= TRUE;

      wait;

   end process COMMAND_INPUT;

------------------------------------------------------------------------
-- TRACE OUTPUT process
-- This process writes out the outputs of the Alarm Clock
-- to an external text file
------------------------------------------------------------------------
   TRACE_OUTPUT: process 
      file TRACEFILE   : text is out "trace.txt";
      variable L       : line;
      variable READING : string(1 to 4);

      -- seven segment declarations would be better placed in a package!
      -- constants for the segments to light for each digit 0 to 9
      constant ZERO_SEG  : std_logic_vector(6 downto 0):= "0111111";
      constant ONE_SEG   : std_logic_vector(6 downto 0):= "0000110";
      constant TWO_SEG   : std_logic_vector(6 downto 0):= "1011011";
      constant THREE_SEG : std_logic_vector(6 downto 0):= "1001111";
      constant FOUR_SEG  : std_logic_vector(6 downto 0):= "1100110";
      constant FIVE_SEG  : std_logic_vector(6 downto 0):= "1101101";
      constant SIX_SEG   : std_logic_vector(6 downto 0):= "1111101";
      constant SEVEN_SEG : std_logic_vector(6 downto 0):= "0000111";
      constant EIGHT_SEG : std_logic_vector(6 downto 0):= "1111111";
      constant NINE_SEG  : std_logic_vector(6 downto 0):= "1101111";
      constant ERROR_SEG : std_logic_vector(6 downto 0):= "1111100"; 

      function SEVENSEG2CHAR (SEVENSEG : std_logic_vector(6 downto 0))
                                          return character is
         variable CHAR : character;
      begin
      case SEVENSEG is
          when ZERO_SEG =>
            CHAR := '0';
          when ONE_SEG =>
            CHAR := '1';
          when TWO_SEG =>
            CHAR := '2';
          when THREE_SEG =>
            CHAR := '3';
          when FOUR_SEG =>
            CHAR := '4';
          when FIVE_SEG =>
            CHAR := '5';
          when SIX_SEG =>
            CHAR := '6';
          when SEVEN_SEG =>
            CHAR := '7';
          when EIGHT_SEG =>
            CHAR := '8';
          when NINE_SEG =>
            CHAR := '9';
          when others => 
            CHAR := '-';
         end case;
         return CHAR;
      end SEVENSEG2CHAR;

   begin
       wait on DISPLAY_MS_HR, DISPLAY_LS_HR, DISPLAY_MS_MIN, DISPLAY_LS_MIN;

       -- Build up the line to be written out:
       -- first print current simulation time, then a space,...
       write(L, NOW);
       write(L, ' ');

       -- Build up the line to be written out:
       -- write the value of the DISPLAY, type-converting to CHARACTER

       READING := (SEVENSEG2CHAR(DISPLAY_MS_HR), SEVENSEG2CHAR(DISPLAY_LS_HR),
                   SEVENSEG2CHAR(DISPLAY_MS_MIN), SEVENSEG2CHAR(DISPLAY_LS_MIN));
       
       write(L, READING);

       -- signals for debug
       LS_MIN <= READING(4);
       MS_MIN <= READING(3);
       LS_HR  <= READING(2);
       MS_HR  <= READING(1);

       -- write out the status of SOUND_ALARM
       write(L, ' ');
       write(L, STDU2CHAR(SOUND_ALARM));

       -- write out the line you have built-up to the output file
       writeline(TRACEFILE, L);        

    end process TRACE_OUTPUT;

end TEST;                

configuration CFG_T_A_CLK of T_A_CLK is
for TEST
end for;    
end CFG_T_A_CLK;