alreg.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- Alreg.vhd
-- Register bank to store alarm time 
--
--------------------------------------------------------------- 

Library IEEE;
use IEEE.Std_Logic_1164.all; 

entity ALREG is
   port(NEW_ALARM_TIME        : in std_logic_vector (3 downto 0);
        LOAD_NEW_A            : in std_logic;
        CLK                   : in std_logic;
        RESET                 : in std_logic;
        ALARM_TIME            : out std_logic_vector (3 downto 0));
end ALREG;

architecture RTL of ALREG is
begin

   -----------------------------------------------------------
   -- Single clocked process to create the four registers.
   -- This coding style must be conformed to synthesize
   -- the registers and for maximum portability
   -----------------------------------------------------------
   process(CLK, RESET) 
   begin
      if (RESET = '1') then
         ALARM_TIME <= "0000";
      elsif (CLK'event and CLK='1') then
         if LOAD_NEW_A = '1' then
            ALARM_TIME <= NEW_ALARM_TIME;
         end if;
      end if;
   end process;

end RTL;