t_ddrv.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_ddrv.vhd
-- Test bench for the bit based display driver 
-- 
--------------------------------------------------------------- 

Library IEEE;
use IEEE.Std_Logic_1164.all; 
use work.P_DISP1.all;

entity T_DDRV is
end T_DDRV;  

architecture TEST of T_DDRV is

   component DDRV
   port ( ALARM_TIME, CURRENT_TIME  : in std_logic_vector(3 downto 0);
          SHOW_A                    : in std_logic;
          SOUND_ALARM               : out std_logic;
          DISPLAY                   : out std_logic_vector(6 downto 0)
        );
   end component;

   signal ALARM_TIME, CURRENT_TIME  : std_logic_vector(3 downto 0);
   signal SHOW_A                    : std_logic;
   signal SOUND_ALARM               : std_logic;
   signal DISPLAY                   : std_logic_vector(6 downto 0);

begin

   uut : DDRV port map (ALARM_TIME, 
                        CURRENT_TIME,
                        SHOW_A,
                        SOUND_ALARM,
                        DISPLAY);

---------------------------------------
-- Process to generate stimulus ...
---------------------------------------

   STIMULUS: process
   begin
      ALARM_TIME    <= "0000";
      CURRENT_TIME  <= "0000";
      SHOW_A       <= '0';
      wait for 10 ns;

      ALARM_TIME    <= "0010";
      CURRENT_TIME  <= "0111";
      SHOW_A       <= '0';
      wait for 10 ns;

      SHOW_A       <= '1';
      wait for 10 ns;

      CURRENT_TIME  <= "0011";
      SHOW_A       <= '1';
      wait for 10 ns;

      CURRENT_TIME  <= "1000";
      SHOW_A       <= '0';
      wait for 10 ns;

      wait;
   end process STIMULUS;


---------------------------------------
-- 7 Segment Display...
---------------------------------------
   DISP1(DISPLAY);

end TEST;

---------------------------------------
-- configuration...
---------------------------------------

configuration CFG_T_DDRV of T_DDRV is
   for TEST
   end for;
end CFG_T_DDRV;