count4.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- Count4.vhd
-- 4-digit time counter
--------------------------------------------------------------- 


Library IEEE;
use IEEE.Std_Logic_1164.all; 
use IEEE.numeric_std.all;   -- check tool workbooks for compatibility with numeric_std

entity COUNT4 is
   port( NEW_CURRENT_TIME_LS_MIN, 
         NEW_CURRENT_TIME_MS_MIN, 
         NEW_CURRENT_TIME_LS_HR, 
         NEW_CURRENT_TIME_MS_HR  : in std_logic_vector(3 downto 0);
         LOAD_NEW_C              : in std_logic;
         CLK, ONE_MINUTE, 
         RESET                   : in std_logic;
         CURRENT_TIME_LS_MIN,   
         CURRENT_TIME_MS_MIN,  
         CURRENT_TIME_LS_HR,    
         CURRENT_TIME_MS_HR      : out std_logic_vector(3 downto 0)
        );
end COUNT4 ;

architecture RTL of COUNT4 is
   
   constant ZERO : unsigned(3 downto 0) := "0000";
   constant ONE  : unsigned(3 downto 0) := "0001";
   constant TWO  : unsigned(3 downto 0) := "0010";
   constant THREE: unsigned(3 downto 0) := "0011";
   constant FIVE : unsigned(3 downto 0) := "0101";
   constant NINE : unsigned(3 downto 0) := "1001";

   -- internal signals defined as unsigned types to use
   -- numeric_std package for arithmetic.
   -- Note: internal variables could also be used
   signal LS_MIN, MS_MIN, LS_HR, MS_HR : unsigned(3 downto 0);

begin

   TIME_COUNTER:
   process(CLK, RESET)
   begin
   
      if (RESET = '1') then
         LS_MIN <= "0000";
         MS_MIN <= "0000";
         LS_HR <= "0000"; 
         MS_HR <= "0000";
      elsif (CLK'event and CLK='1') then

         if (LOAD_NEW_C = '1') then
            -- capture new current time (convert std_logic_vector to unsigned)
            LS_MIN <= unsigned(NEW_CURRENT_TIME_LS_MIN);
            MS_MIN <= unsigned(NEW_CURRENT_TIME_MS_MIN);
            LS_HR <=  unsigned(NEW_CURRENT_TIME_LS_HR); 
            MS_HR <=  unsigned(NEW_CURRENT_TIME_MS_HR);

         else if ONE_MINUTE = '1' then  -- count when enabled
         -- the algorithm starts at the minutes, and ripples upwards
         -- notice tests are all "=" - see what happens if set 
         -- current time as 79:79!
                 if LS_MIN = NINE then
                    LS_MIN <= ZERO;
                    if MS_MIN = FIVE then
                       MS_MIN <= ZERO;
                       -- deal with special case of 23:59 -> 00:00
                       if MS_HR = TWO and LS_HR = THREE then
                          MS_HR <= ZERO;
                          LS_HR <= ZERO;
                       elsif LS_HR = NINE then
                          MS_HR <= MS_HR + ONE;
                          LS_HR <= ZERO;
                       else 
                          LS_HR <= LS_HR + ONE;
                       end if;
                    else 
                      MS_MIN <= MS_MIN + ONE;
                    end if;
                 else 
                   LS_MIN <= LS_MIN + ONE;
                 end if;
              end if; -- (ONE_MINUTE = '1')
         end if; -- (LOAD_NEW_C = '1')
      end if; -- CLK'event

   end process TIME_COUNTER;

   -- concurrent signal assignment to update outputs
   -- from 
   CURRENT_TIME_LS_MIN <= std_logic_vector(LS_MIN);
   CURRENT_TIME_MS_MIN <= std_logic_vector(MS_MIN);
   CURRENT_TIME_LS_HR <= std_logic_vector(LS_HR);
   CURRENT_TIME_MS_HR <= std_logic_vector(MS_HR);

end RTL ;