alreg4.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- Alreg4.vhd
-- Array based register bank to store 4 digit alarm time, instantiating
-- 4 single digit registers (Alreg.vhd) (Lab 13) 
-- 
--------------------------------------------------------------- 

Library IEEE;
use IEEE.Std_Logic_1164.all; 

entity ALREG4 is
   port(KEYPAD_LS_MIN,
	      KEYPAD_MS_MIN,
	      KEYPAD_LS_HR,
	      KEYPAD_MS_HR          : in std_logic_vector (3 downto 0);
        LOAD_NEW_A            : in std_logic;
        CLK                   : in std_logic;
        RESET                 : in std_logic;
        ALARM_TIME_LS_MIN,
	      ALARM_TIME_MS_MIN,
	      ALARM_TIME_LS_HR,      
	      ALARM_TIME_MS_HR      : out std_logic_vector (3 downto 0));
end ALREG4;

architecture RTL of ALREG4 is

component ALREG 
   port(NEW_ALARM_TIME        : in std_logic_vector (3 downto 0);
        LOAD_NEW_A            : in std_logic;
        CLK                   : in std_logic;
        RESET                 : in std_logic;
        ALARM_TIME            : out std_logic_vector (3 downto 0));
end component;

begin

U1 : ALREG port map (KEYPAD_LS_MIN, LOAD_NEW_A, CLK, RESET, ALARM_TIME_LS_MIN);

U2 : ALREG port map (KEYPAD_MS_MIN, LOAD_NEW_A, CLK, RESET, ALARM_TIME_MS_MIN);

U3 : ALREG port map (KEYPAD_LS_HR, LOAD_NEW_A, CLK, RESET, ALARM_TIME_LS_HR);

U4 : ALREG port map (KEYPAD_MS_HR, LOAD_NEW_A, CLK, RESET, ALARM_TIME_MS_HR);

end RTL;