t_alreg.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_alreg.vhd
-- Test bench for register bank to store alarm time
--  
--------------------------------------------------------------- 

Library IEEE;
use IEEE.Std_Logic_1164.all; 

entity T_ALREG is
end T_ALREG;

architecture TEST of T_ALREG is
   component ALREG
   port( NEW_ALARM_TIME        : in std_logic_vector (3 downto 0);
         LOAD_NEW_A            : in std_logic;
         CLK                   : in std_logic;
         RESET                 : in std_logic;
         ALARM_TIME            : out std_logic_vector (3 downto 0)
        );
   end component;

   signal NEW_ALARM_TIME        : std_logic_vector (3 downto 0);
   signal LOAD_NEW_A            : std_logic;
   signal ALARM_TIME            : std_logic_vector (3 downto 0);
   signal CLK                   : std_logic := '0';
   signal RESET                 : std_logic;
 
   constant PERIOD              : time := 10 ns;

begin

   ---------------------------------------------
   -- instantiate UUT
   ---------------------------------------------
   uut : ALREG port map(
         NEW_ALARM_TIME,
         LOAD_NEW_A,
         CLK,
         RESET,
         ALARM_TIME);

   ---------------------------------------------
   -- infinite clock generator 
   ---------------------------------------------
      CLK <= not CLK after PERIOD/2;
            
   --------------------------------------------------
   -- Stimulus   
   -------------------------------------------------
   STIMULUS : process
   begin
      -- pulse reset
      RESET <= '0';
      wait for 2 * PERIOD;
      RESET <= '1';
      wait for PERIOD;
      RESET <= '0';

      LOAD_NEW_A <= '0';
      wait for PERIOD;
     
      LOAD_NEW_A <= '1';
      NEW_ALARM_TIME <= "0001";
      wait for PERIOD;

      LOAD_NEW_A <= '0';
      NEW_ALARM_TIME <= "0000";
      wait for 2 * PERIOD;

      wait;
     
   end process STIMULUS;

end TEST;

configuration CFG_T_ALREG of T_ALREG is
   for TEST
   end for;
end CFG_T_ALREG;