t_decode.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_decode.vhd
-- Test bench for 10 to 4 decoder to decode keys pressed 
-- 
--------------------------------------------------------------- 
library IEEE;
use IEEE.Std_Logic_1164.all;

entity T_DECODE is
end T_DECODE;

architecture  TEST of T_DECODE is

   component DECODE
   port (KEYPAD  : in std_logic_vector (0 to 9);
         VALUE   : out std_logic_vector (3 downto 0)
	);
   end component;

   signal KEYPAD  : std_logic_vector (0 to 9);
   signal VALUE   : std_logic_vector (3 downto 0);

begin

   --------------------------------------------------
   -- Instantiate UUT
   --------------------------------------------------

   UUT : DECODE port map (KEYPAD, VALUE);

   --------------------------------------------------
   -- Stimulus:
   --------------------------------------------------
   STIMULUS: process
   begin

      KEYPAD <= "1000000000";
      for i in 1 to 9 loop
         wait for 10 ns;
         KEYPAD(i) <= '1';
         KEYPAD(i-1) <= '0';
      end loop;

      wait for 10 ns;
      KEYPAD <= "1111111111";

      wait;

   end process STIMULUS;

end TEST;

--------------------------------------------------
-- Configuration...
--------------------------------------------------
configuration CFG_T_DECODE of T_DECODE is
   for TEST
   end for;
end CFG_T_DECODE;