t_ddrv4.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_ddrv4.vhd
-- Test bench for the array based display driver
-- 
--------------------------------------------------------------- 

Library IEEE;
use IEEE.Std_Logic_1164.all; 

-- Consult your tool workbooks to check compatibility with numeric_std
-- arithmetic package.
use IEEE.numeric_std.all;
use work.P_DISP4.all;

entity T_DDRV4 is
end T_DDRV4;  

architecture TEST of T_DDRV4 is

 component DDRV4
   port ( ALARM_TIME_LS_MIN, CURRENT_TIME_LS_MIN  : in std_logic_vector(3 downto 0);
          ALARM_TIME_MS_MIN, CURRENT_TIME_MS_MIN  : in std_logic_vector(3 downto 0);
          ALARM_TIME_LS_HR, CURRENT_TIME_LS_HR    : in std_logic_vector(3 downto 0);
          ALARM_TIME_MS_HR, CURRENT_TIME_MS_HR    : in std_logic_vector(3 downto 0);
          SHOW_A                    : in std_logic;
          SOUND_ALARM               : out std_logic;
          DISPLAY_LS_MIN            : out std_logic_vector(6 downto 0);
          DISPLAY_MS_MIN            : out std_logic_vector(6 downto 0);
          DISPLAY_LS_HR             : out std_logic_vector(6 downto 0);
          DISPLAY_MS_HR             : out std_logic_vector(6 downto 0));
 end component;

   signal ALARM_TIME_LS_MIN, CURRENT_TIME_LS_MIN, 
          ALARM_TIME_MS_MIN, CURRENT_TIME_MS_MIN,  
          ALARM_TIME_LS_HR, CURRENT_TIME_LS_HR, 
          ALARM_TIME_MS_HR, CURRENT_TIME_MS_HR    : std_logic_vector(3 downto 0):="0000";
   signal SHOW_A, SOUND_ALARM                     : std_logic;
   signal DISPLAY_LS_MIN, DISPLAY_MS_MIN,
          DISPLAY_LS_HR,  DISPLAY_MS_HR           : std_logic_vector(6 downto 0);

begin

   uut : DDRV4 port map (ALARM_TIME_LS_MIN, CURRENT_TIME_LS_MIN,
                         ALARM_TIME_MS_MIN, CURRENT_TIME_MS_MIN,
                         ALARM_TIME_LS_HR, CURRENT_TIME_LS_HR,
                         ALARM_TIME_MS_HR, CURRENT_TIME_MS_HR,
                         SHOW_A, SOUND_ALARM,               
                         DISPLAY_LS_MIN, DISPLAY_MS_MIN,            
                         DISPLAY_LS_HR, DISPLAY_MS_HR);

---------------------------------------
-- Process to generate stimulus ...
---------------------------------------

   STIMULUS: process
   begin

      SHOW_A  <= '0';
      ALARM_TIME_MS_HR   <= "0000";
      ALARM_TIME_LS_HR   <= "0000";
      ALARM_TIME_MS_MIN  <= "0101";
      ALARM_TIME_LS_MIN  <= "1001";  -- ie 00:59
      SHOW_A  <= '1';
      wait for 10 ns;

      SHOW_A  <= '0';
      wait for 10 ns;

      for MS_HOUR in 0 to 1 loop
         for LS_HOUR in 0 to 9 loop
            for MS_MIN in 0 to 5 loop
               for LS_MIN in 0 to 9 loop
		             -- Following conversion sequence uses the function to_unsigned
                 -- from the package numeric_std to convert an integer (loop variable)
                 -- into an unsigned 4-bit vector, and then uses implicit type conversion
                 -- (see day 4 - Advanced Data Types) to produce a std_logic_vector type
                  CURRENT_TIME_MS_HR  <= std_logic_vector(to_unsigned(MS_HOUR,4));
		              CURRENT_TIME_LS_HR  <= std_logic_vector(to_unsigned(LS_HOUR,4));
		              CURRENT_TIME_MS_MIN <= std_logic_vector(to_unsigned(MS_MIN,4));
		              CURRENT_TIME_LS_MIN <= std_logic_vector(to_unsigned(LS_MIN,4));
                  wait for 10 ns;
               end loop;
            end loop;
        end loop;
      end loop;

      wait;
   end process STIMULUS;
 
---------------------------------------
-- Seven Segment Display...
---------------------------------------
   DISP4(DISPLAY_MS_HR, DISPLAY_LS_HR, DISPLAY_MS_MIN, DISPLAY_LS_MIN);

end TEST;

---------------------------------------
-- configuration...
---------------------------------------

configuration CFG_T_DDRV4 of T_DDRV4 is
   for TEST
   end for;
end CFG_T_DDRV4;