t_a_fsm2.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_a_fsm2.vhd
-- Testbench for the Alarm Controller and Keyscan blocks (Lab 12)
--
----------------------------------------------------

Library IEEE;
use IEEE.Std_Logic_1164.all; 
use std.textio.all;

use work.P_ALARM_TEST.all;   -- package holds procedures defining commands

entity T_A_FSM2 is
end T_A_FSM2;

architecture TEST of T_A_FSM2 is

signal CLK                       : std_logic := '0';
signal RESET                     : std_logic := '0';
signal ONE_SEC_PULSE             : std_logic := '0'; 
signal ALARM_BUTTON, TIME_BUTTON : std_logic := '0';
signal DKEY, ROWS                : std_logic_vector(3 downto 0);
signal COLUMNS                   : std_logic_vector(2 downto 0);
signal KEY_BUFF_0, KEY_BUFF_1,
       KEY_BUFF_2, KEY_BUFF_3    : std_logic_vector(3 downto 0);
signal LOAD_NEW_A, SHOW_A,
       SHOW_NEW_TIME, LOAD_NEW_C,
       SHIFT                     : std_logic;
signal SIM_END                   : boolean := FALSE;
signal KEY                       : T_KEYPAD;

   component A_FSM2
   port( CLK            : in std_logic;
         RESET          : in std_logic;
         KEY            : in std_logic_vector(3 downto 0);
         ALARM_BUTTON   : in std_logic;
         TIME_BUTTON    : in std_logic;
         ONE_SECOND     : in std_logic;
         LOAD_NEW_A     : out std_logic;
         SHOW_A         : out std_logic;
         SHOW_NEW_TIME  : out std_logic;
         LOAD_NEW_C     : out std_logic;
         SHIFT          : out std_logic);
   end component;

   component KEYSCAN
   port( CLK            : in std_logic;
         RESET          : in std_logic;
         SHIFT          : in std_logic;
         ROWS           : in std_logic_vector(3 downto 0);
         COLUMNS        : out std_logic_vector(2 downto 0);
         KEY            : out std_logic_vector(3 downto 0);
         KEY_BUFFER_0   : out std_logic_vector(3 downto 0);
         KEY_BUFFER_1   : out std_logic_vector(3 downto 0);
         KEY_BUFFER_2   : out std_logic_vector(3 downto 0);
         KEY_BUFFER_3   : out std_logic_vector(3 downto 0);
         TIME_BUTTON    : out std_logic;
         ALARM_BUTTON   : out std_logic);
end component;

component KEYPAD
 port ( KEY             : in T_KEYPAD;
        COLUMNS         : in std_logic_vector(2 downto 0);
        ROWS            : out std_logic_vector(3 downto 0));
end component;

begin 
   -- Generate CLK and Reset waveforms
   CLK <= not CLK after PERIOD/2 when SIM_END = FALSE else '0'; 
   RESET <= '1' after PERIOD, '0' after 3*PERIOD; 

   -- Generate a true one-second pulse
   process
   begin
      while SIM_END = FALSE loop
         ONE_SEC_PULSE <= '1';
         wait for PERIOD;
         ONE_SEC_PULSE <= '0';
         wait for 255*PERIOD;
      end loop;
      wait;
   end process;

   -- Instantiate the block under test
   CONTROL: A_FSM2
   port map( CLK           => CLK,
             RESET         => RESET,
             KEY           => DKEY,
             ALARM_BUTTON  => ALARM_BUTTON,
             TIME_BUTTON   => TIME_BUTTON,
             ONE_SECOND    => ONE_SEC_PULSE,
             LOAD_NEW_A    => LOAD_NEW_A,
             SHOW_A        => SHOW_A,
             SHOW_NEW_TIME => SHOW_NEW_TIME,
             LOAD_NEW_C    => LOAD_NEW_C,
             SHIFT         => SHIFT);

   U_KEYSCAN: KEYSCAN
   port map( CLK           => CLK,
             RESET         => RESET,
             SHIFT         => SHIFT,
             ROWS          => ROWS,
             COLUMNS       => COLUMNS,
             KEY           => DKEY,
             KEY_BUFFER_0  => KEY_BUFF_0,
             KEY_BUFFER_1  => KEY_BUFF_1,
             KEY_BUFFER_2  => KEY_BUFF_2,
             KEY_BUFFER_3  => KEY_BUFF_3,
             TIME_BUTTON   => TIME_BUTTON,
             ALARM_BUTTON  => ALARM_BUTTON);

   U_KEYPAD: KEYPAD
   port map( KEY           => KEY,
             COLUMNS       => COLUMNS,
             ROWS          => ROWS);

------------------------------------------------------------------------
-- COMMAND INPUT process
-- This process reads command strings from  the test file "command.txt"
-- and generates input stimulus to the block under test, depending upon
-- which command is read in. The commands are:
--
-- SETAL DDDD -- set alarm <time> 
-- SETTI DDDD -- set time  <time>
-- SHWAL      -- show alarm
-- COUNT D    -- advance the clock by <clock_cycles>
-- KTOUT      -- test the keypad timeout
--
-- (D = integer ascii character in range 0-9)
------------------------------------------------------------------------
   COMMAND_INPUT: process 
      file COMFILE                   : text is in "command.txt";
      variable L                     : line;
      variable CMD                   : string(1 to 5);
      variable SETTING               : string(1 to 4);
      variable CYCLES, SEPARATOR     : character;
   begin
      -- if there are still lines to read in the text file ...
      while not ENDFILE(COMFILE) loop

         -- read in next line from text file, then read the first text string
         -- from the line and call this CMD.
         readline(COMFILE, L);
         read (L, CMD);

         -- Depending on what the command is, read in any extra information
         -- from the line read from the file and then "do" the command
         case CMD is
            when "SHALM" => DO_SHALM(KEY);
            when "SETAL" => read (L, SEPARATOR);
                            read (L, SETTING);
                            DO_SETAL(SETTING, KEY);
            when "SETTI" => read (L, SEPARATOR);
                            read (L, SETTING);
                            DO_SETTI(SETTING, KEY);
            when "COUNT" => read(L, SEPARATOR);
                            read(L, CYCLES);
                            DO_COUNT(CYCLES);
            when "KTOUT" => DO_KTOUT(KEY);
            when others => assert FALSE report "Unrecognised Instruction"
                              severity FAILURE;
         end case;

      end loop;

      -- No new lines to read from file, so report simulation complete and
      -- stop clock generator with SIM_END signal
      assert FALSE report "Simulation complete" severity NOTE;
      SIM_END <= TRUE;

      wait;

   end process COMMAND_INPUT;

------------------------------------------------------------------------
-- COMMAND INPUT process
-- This process reads command strings from  the test file "command.txt"
-- and generates input stimulus to the block under test, depending upon
-- which command is read in
------------------------------------------------------------------------
   TRACE_OUTPUT: process 
      type T_INT_ARRAY is array (3 downto 0) of integer range 0 to 9;
      file TRACEFILE          : text is out "trace.txt";
      variable L              : line;
      variable CTRL_OUTPUTS   : std_logic_vector(1 to 4);
      variable STORED_KEYS    : T_INT_ARRAY;

      function VEC2INT (VEC : std_logic_vector(3 downto 0))
                                          return integer is
         variable INT : integer;
      begin
         case VEC is
            when "0000" => INT := 0;
            when "0001" => INT := 1;
            when "0010" => INT := 2;
            when "0011" => INT := 3;
            when "0100" => INT := 4;
            when "0101" => INT := 5;
            when "0110" => INT := 6;
            when "0111" => INT := 7;
            when "1000" => INT := 8;
            when "1001" => INT := 9;
            when others => 
         end case;
         return INT;
      end VEC2INT;

    begin
        wait until CLK'event and CLK = '1';

       -- Build up the line to be written out:
       -- first print current simulation time, then a space,...
        write(L, NOW);
        write(L, ' ');

       -- ... then type-convert the state-machine outputs and add them
       -- to the line to be written.
        CTRL_OUTPUTS := (LOAD_NEW_A & SHOW_A & SHOW_NEW_TIME & LOAD_NEW_C);
        for I in CTRL_OUTPUTS'range loop
            write(L, STDU2CHAR(CTRL_OUTPUTS(I)));
        end loop;

        -- assign STORED_KEYS with the type-converted KEY_BUFF values
        STORED_KEYS := (VEC2INT(KEY_BUFF_3), VEC2INT(KEY_BUFF_2),
                        VEC2INT(KEY_BUFF_1), VEC2INT(KEY_BUFF_0));
        -- write another space to separate the columns then write out
        -- the array of integers from the keypad store
        write(L, ' ');
        for I in STORED_KEYS'range loop
           write(L, STORED_KEYS(I));
        end loop;

        -- write out the line you have built-up to the output file
        writeline(TRACEFILE, L);        

    end process TRACE_OUTPUT;

end TEST;                


configuration CFG_T_A_FSM2 of T_A_FSM2 is
for TEST
end for;
end CFG_T_A_FSM2;