dismux1.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- Dismux1.vhd
-- Display multiplexer
--
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Library IEEE;
use IEEE.Std_Logic_1164.all;

entity DISMUX is
port ( ALARM_TIME, CURRENT_TIME  : in std_logic_vector (3 downto 0);
       SHOW_A                    : in std_logic;
       DISPLAY_TIME              : out std_logic_vector (3 downto 0));
end DISMUX;  

architecture RTL of DISMUX is
begin

  -- ALARM_TIME, CURRENT_TIME and SHOW_A must all be in the
  -- process sensitivity list

  MUX: process (ALARM_TIME, CURRENT_TIME, SHOW_A)
  begin
    if (SHOW_A = '1') then
      DISPLAY_TIME <= ALARM_TIME;
    else
      DISPLAY_TIME <= CURRENT_TIME;
    end if;
  end process MUX;

end RTL;