a_fsm.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- A_fsm.vhd
-- Alarm clock controller
--
----------------------------------------------------


Library IEEE;
use IEEE.Std_Logic_1164.all; 


entity A_FSM is
   port( CLK            : in std_logic;
         RESET          : in std_logic;
         KEY            : in std_logic_vector(3 downto 0);
         ALARM_BUTTON   : in std_logic;
         TIME_BUTTON    : in std_logic;
         ONE_SECOND     : in std_logic;
         LOAD_NEW_A     : out std_logic;
         SHOW_A         : out std_logic;
         SHOW_NEW_TIME  : out std_logic;
         LOAD_NEW_C     : out std_logic);
end A_FSM;

architecture RTL of A_FSM is

   type T_STATE is (SHOW_TIME,           -- clock just counts
                    KEY_ENTRY,           -- in key entry mode
                    SHOW_ALARM,          -- shows time alarm is set
                    SET_ALARM_TIME,      -- sets alarm time
                    SET_CURRENT_TIME);   -- sets current time
                    
   signal STATE : T_STATE;               -- holds the internal state of block
   signal TIMEOUT  : integer range 0 to 10;  -- counts the keypad timeout

begin

   STATE_MACHINE: process (CLK, RESET)
   begin
      if RESET = '1' then
         STATE <= SHOW_TIME;
         TIMEOUT <= 0;
      elsif CLK'event AND CLK = '1' then
         case STATE is
            when SHOW_TIME => 
               if ALARM_BUTTON = '1' then 
                  STATE <= SHOW_ALARM;
               elsif KEY /= "1010" then
                  STATE <= KEY_ENTRY;
                  TIMEOUT <= 10;
               end if;
            when KEY_ENTRY =>
               if ALARM_BUTTON = '1' then
                  STATE <= SET_ALARM_TIME;
               elsif TIME_BUTTON = '1' then
                  STATE <= SET_CURRENT_TIME;
               elsif KEY /= "1010" then
                  TIMEOUT <= 10;
               elsif TIMEOUT = 0 then
                  STATE <= SHOW_TIME;
               elsif ONE_SECOND = '1' then
                  TIMEOUT <= TIMEOUT - 1;
               end if;
            when SHOW_ALARM => 
               if ALARM_BUTTON = '0' then
                  STATE <= SHOW_TIME;
               end if;
            when SET_ALARM_TIME =>
               STATE <= SHOW_TIME;
            when SET_CURRENT_TIME =>
               STATE <= SHOW_TIME;
            when others => STATE <= SHOW_TIME;
              -- no meaning until mapped to logic!
         end case;
      end if; -- closes asynch clock process construct

   end process STATE_MACHINE;
    
   -- Now assign outputs depending on internal state ...

   SHOW_NEW_TIME <= '1' when STATE = KEY_ENTRY else '0';

   SHOW_A <= '1' when STATE = SHOW_ALARM else '0';

   LOAD_NEW_A <= '1' when STATE = SET_ALARM_TIME else '0';

   LOAD_NEW_C <= '1' when STATE = SET_CURRENT_TIME else '0';

end RTL;