t_timeg.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_timegen.vhd
-- Test bench for the Alarm Clock Timing Generator
--
--------------------------------------------------------------- 

library IEEE;                                -- WHAT LIBRARY?
use IEEE.Std_Logic_1164.all; 

entity T_TIMEG is
end T_TIMEG;
                                             -- SPECIFY THE ENTITY
architecture TEST of T_TIMEG is

   component TIMEGEN
   port( CLK             : in std_logic;
         RESET           : in std_logic;
         STOPWATCH       : in std_logic;
         ONE_SECOND      : out std_logic;
         ONE_MINUTE      : out std_logic);
   end component;

   signal ONE_SECOND, ONE_MINUTE  : std_logic;
   signal STOPWATCH, RESET        : std_logic;
   signal CLK                     : std_logic:= '0';   -- ANY INITIAL VALUE NEEDED?

   constant PERIOD     : time := 10 ns;

begin

   ---------------------------------------------
   -- instantiate UUT
   ---------------------------------------------

   uut:  TIMEGEN port map (CLK, RESET, STOPWATCH, ONE_SECOND, ONE_MINUTE);  -- COMPLETE THE PORT MAP

   ---------------------------------------------
   -- infinite clock generator 
   ---------------------------------------------

   CLK <=  not(CLK) after PERIOD/2;                         -- COMPLETE CLOCK GENERATOR

   --------------------------------------------------
   -- Stimulus: 
   -------------------------------------------------
   STIMULUS : process
   begin

      STOPWATCH <= '0';
      RESET <= '0';
      wait for 2 * PERIOD;
      RESET <= '1';
      wait for PERIOD;
      RESET <= '0';

      -- STOPWATCH = '0', therefore after 256 clock cycles
      -- we expect ONE_SECOND = ONE_MINUTE = '1'. Count 1024
      -- clock cycles to see 4 ONE_SECOND cycles
      for i in 1 to 1024 loop
        wait until clk = '1';
          assert (ONE_SECOND nand ONE_MINUTE) = '1'
            report "ONE_SECOND and ONE_MINUTE active during STOPWATCH = '0'"
            severity note;
      end loop;

      STOPWATCH <= '1';
      -- STOPWATCH = '0', therefore we expect 15360 clock cycles
      -- and 60 ONE_SECOND pulses until ONE_MINUTE = '1'. Count 
      -- 30720 clock cycles to see 2 ONE_MINUTE cycles
      for i in 1 to 30720 loop
        wait until clk = '1';
          assert ONE_SECOND = '0'
            report "ONE_SECOND active during STOPWATCH = '1'"
            severity note;
          assert ONE_MINUTE = '0'
            report "ONE_MINUTE active during STOPWATCH = '1'"
            severity note;
      end loop;

      wait;

   end process STIMULUS;

end TEST;

configuration CFG_T_TIMEG of T_TIMEG is
   for TEST
   end for;
end CFG_T_TIMEG;