t_count4.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_count4.vhd
-- Test bench for the 4-digit counter 
--
--------------------------------------------------------------- 

Library IEEE;
use IEEE.Std_Logic_1164.all; 

entity T_COUNT4 is
end T_COUNT4 ;

architecture TEST of T_COUNT4 is
   component COUNT4
      port(-- 4 signals             :  in std_logic_vector(3 downto 0);
           LOAD_NEW_C               : in std_logic;
           CLK, ONE_MINUTE, RESET   : in std_logic;
           -- 4 signals             :  out std_logic_vector(3 downto 0));
   end component;

  signal -- 4 signals  : std_logic_vector(3 downto 0):= "0000";
  signal LOAD_NEW_C                 : std_logic:= '0';
  signal CLK                        : std_logic:= '0';
  signal RESET                      : std_logic:= '0';
  signal ONE_MINUTE                 : std_logic:= '0';
  signal -- 4 signals   : std_logic_vector(3 downto 0):= "0000";

   constant PERIOD : time := 10 ns;

begin

   ---------------------------------------------
   -- instantiate UUT
   ---------------------------------------------

   uut : COUNT4 port map(
                      -- 4 signals
                      LOAD_NEW_C,
                      CLK, ONE_MINUTE, RESET,
                      -- 4 signals);

   ---------------------------------------------
   -- infinite clock generator 
   ---------------------------------------------

      CLK <= not CLK after PERIOD/2;

   ---------------------------------------------
   -- one_minute generator - make equal to twice CLK to
   -- make testing quicker
   ---------------------------------------------

      ONE_MINUTE <= not ONE_MINUTE after PERIOD;

   --------------------------------------------------
   -- Stimulus: we want to
   --   1. pulse reset
   --   2. watch it count to the LS_MIN rollover
   --   3. Load 00:58 and watch the next rollover
   --   4. Load 09:58 and watch the rollover
   --   5. Load 11:58 and watch the rollover
   --   6. Load 23:58 and watch the rollover
   --   7. Just let it count
   -------------------------------------------------
   STIMULUS : process
   begin
      -- pulse reset

      -- synchronise changes with clock...
      wait for period/2;


   end process STIMULUS;


end TEST;

configuration CFG_T_COUNT4 of T_COUNT4 is
   for TEST
   end for;
end CFG_T_COUNT4;