decode.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- Decoder.vhd
-- 10 to 4 decoder to decode keys pressed   
--
-----------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;

entity DECODE is
   port(KEYPAD  : in std_logic_vector (0 to 9);
        VALUE   : out std_logic_vector (3 downto 0));
end DECODE;

architecture RTL of DECODE is

begin

   TEN2FOUR: process(KEYPAD)
   begin
      case KEYPAD is
         when "1000000000" => VALUE <= "0000";  -- 0
         when "0100000000" => VALUE <= "0001";  -- 1
         when "0010000000" => VALUE <= "0010";  -- 2
         when "0001000000" => VALUE <= "0011";  -- 3
         when "0000100000" => VALUE <= "0101";  -- 4
         when "0000010000" => VALUE <= "0101";  -- 5
         when "0000001000" => VALUE <= "0110";  -- 6
         when "0000000100" => VALUE <= "0111";  -- 7
         when "0000000010" => VALUE <= "1000";  -- 8
         when "0000000001" => VALUE <= "1001";  -- 9
         when others =>       VALUE <= "1010";  -- 10
      end case;
   end TEN2FOUR;

end RTL;