ddrv4.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- Ddrv4.vhd
-- Array based display driver instantiating 4 bit based display drivers
-- (Ddrv.vhd)
-- 
--------------------------------------------------------------- 

Library IEEE;
use IEEE.Std_Logic_1164.all; 

entity DDRV4 is
port ( ALARM_TIME_LS_MIN, CURRENT_TIME_LS_MIN  : in std_logic_vector(3 downto 0);
       ALARM_TIME_MS_MIN, CURRENT_TIME_MS_MIN  : in std_logic_vector(3 downto 0);
       ALARM_TIME_LS_HR, CURRENT_TIME_LS_HR    : in std_logic_vector(3 downto 0);
       ALARM_TIME_MS_HR, CURRENT_TIME_MS_HR    : in std_logic_vector(3 downto 0);
       SHOW_A                    : in std_logic;
       SOUND_ALARM               : out std_logic;
       DISPLAY_LS_MIN            : out std_logic_vector(6 downto 0);
       DISPLAY_MS_MIN            : out std_logic_vector(6 downto 0);
       DISPLAY_LS_HR             : out std_logic_vector(6 downto 0);
       DISPLAY_MS_HR             : out std_logic_vector(6 downto 0)
     );
end DDRV4;  

architecture RTL of DDRV4 is

  -- Declare component DDRV
  -- Declare any internal signals needed

begin

  -- Instantiate four DDRV components
  -- Compute the SOUND_ALARM signal

end RTL ;