count4.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- Count4.vhd
-- 4-digit time counter
--------------------------------------------------------------- 


Library IEEE;
use IEEE.Std_Logic_1164.all;
-- check tool workbooks for compatibility with numeric_std
use IEEE.numeric_std.all;   

entity COUNT4 is
   port( NEW_CURRENT_TIME_LS_MIN, 
         NEW_CURRENT_TIME_MS_MIN, 
         NEW_CURRENT_TIME_LS_HR, 
         NEW_CURRENT_TIME_MS_HR  : in std_logic_vector(3 downto 0);
         LOAD_NEW_C              : in std_logic;
         CLK, ONE_MINUTE, 
         RESET                   : in std_logic;
         CURRENT_TIME_LS_MIN,   
         CURRENT_TIME_MS_MIN,  
         CURRENT_TIME_LS_HR,    
         CURRENT_TIME_MS_HR      : out std_logic_vector(3 downto 0)
        );
end COUNT4 ;

architecture RTL of COUNT4 is
   
   constant ZERO : unsigned(3 downto 0) := "0000";
   constant ONE  : unsigned(3 downto 0) := "0001";
   constant TWO  : unsigned(3 downto 0) := "0010";
   constant THREE: unsigned(3 downto 0) := "0011";
   constant FIVE : unsigned(3 downto 0) := "0101";
   constant NINE : unsigned(3 downto 0) := "1001";

   -- Declaration of intermediate signal required...
   -- if using numeric_std package, use type unsigned
   


begin

   -- Put your algorithm here!!

   -- if using numeric_std package, convert between 
   -- unsigned signals and std_logic_vector ports as follows:-
   --   ASIGNAL <= unsigned(APORT);
   --   APORT   <= std_logic_vector(ASIGNAL);
   -- Otherwise refer to your workbooks for further guidance

end RTL ;