t_a1_fsm.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
-- *Advanced Lab Exercise A.1*
--
-- T_a1_fsm.vhd
-- Test bench for the Advanced Lab Alarm Clock Controller
--
----------------------------------------------------

Library IEEE;
use IEEE.Std_Logic_1164.all; 
use std.textio.all;
use work.P_ALARM.all;
use work.P_ALARM_TEST.all;   -- package holds procedures defining commands

entity TB_ALARM_CONTROL is
end TB_ALARM_CONTROL;

architecture TEST of TB_ALARM_CONTROL is

signal CLK                       : std_logic := '0';
signal RESET                     : std_logic := '0';
signal ALARM_BUTTON, TIME_BUTTON : std_logic := '0';
signal KEY                       : integer range 0 to 10 := 10;
signal LOAD_NEW_A, SHOW_A,
       SHOW_NEW_TIME, LOAD_NEW_C : std_logic;
signal SIM_END                   : boolean := FALSE;
constant PERIOD                  : time := 20 ns;

begin 
   -- Generate CLK and Reset waveforms
   CLK <= -- generate a clock waveform which can be forced to '0' when
          -- SIM_END = TRUE; 
   RESET <= '1' after PERIOD, '0' after 3*PERIOD; 

   -- Instantiate the block under test here
   
------------------------------------------------------------------------
-- COMMAND INPUT process
-- This process reads command strings from  the test file "command.txt"
-- and generates input stimulus to the block under test, depending upon
-- which command is read in. The commands are:
--
-- SETAL DDDD -- set alarm <time> 
-- SETTI DDDD -- set time  <time>
-- SHWAL      -- show alarm
-- CLOCK D    -- advance the clock by <clock_cycles>
-- KTOUT      -- test the keypad timeout
--
-- (D = integer ascii character in range 0-9)
------------------------------------------------------------------------
   COMMAND_INPUT: process 
      file COMFILE                   : text is in "command.txt";
      variable L                     : line;
      variable CMD                   : string(1 to 5);
      variable SETTING               : string(1 to 4);
      variable CYCLES, SEPARATOR     : character;
   begin
      -- if there are still lines to read in the text file ...
      while not ENDFILE(COMFILE) loop

         -- read in next line from text file, then read the first text string
         -- from the line and call this CMD.

         -- Depending on what the command is, read in any extra information
         -- from the line read from the file and then "do" the command
         case CMD is
            when "SHALM" => -- implement command
            when "SETAL" => read (L, SEPARATOR);
                            read (L, SETTING);
                            DO_SETAL(SETTING, KEY, ALARM_BUTTON, PERIOD);
            when "SETTI" => -- implement command
            when "CLOCK" => -- implement command
            when "KTOUT" => -- implement command
            when others  => -- implement command
         end case;

      end loop;

      -- No new lines to read from file, so report simulation complete and
      -- stop clock generator with SIM_END signal
      assert FALSE report "Simulation complete" severity NOTE;
      SIM_END <= TRUE;

      wait;

   end process COMMAND_INPUT;

------------------------------------------------------------------------
-- COMMAND INPUT process
-- This process reads command strings from  the test file "command.txt"
-- and generates input stimulus to the block under test, depending upon
-- which command is read in
------------------------------------------------------------------------
   TRACE_OUTPUT: process 
      file TRACEFILE          : text is out "trace.txt";
      variable L              : line;

    begin
        wait until CLK'event and CLK = '1';

       -- Build up the line to be written out:
       -- first print current simulation time, then a space,...

       -- ... then add the state-machine outputs to the line 
       -- to be written in the order:
       -- LOAD_NEW_A SHOW_A SHOW_NEW_TIME LOAD_NEW_C
       -- 
       -- You will need to convert std_logic to character to be 
       -- able to write them out

       -- write out the line you have built-up to the output file
        writeline(TRACEFILE, L);

    end process TRACE_OUTPUT;

end TEST;                


configuration CFG_TB_ALARM_CONTROL of TB_ALARM_CONTROL is
for TEST
end for;
end CFG_TB_ALARM_CONTROL;