t_ddrv4.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_ddrv4.vhd
-- Test bench for the array based display driver
-- 
--------------------------------------------------------------- 

Library IEEE;
use IEEE.Std_Logic_1164.all; 

-- Consult your tool workbooks to check compatibility with numeric_std
-- arithmetic package.
use IEEE.numeric_std.all;
use work.P_DISP4.all;

entity T_DDRV4 is
end T_DDRV4;  

architecture TEST of T_DDRV4 is

 component DDRV4
   port ( -- alarm time and current time now have 4 digits

          SHOW_A                    : in std_logic;
          SOUND_ALARM               : out std_logic;
          -- display driver also 4 digits
          );
 end component;

   signal  -- add signals
 
   signal SHOW_A, SOUND_ALARM       : std_logic;


begin

   uut : DDRV4 port map (-- add port map);

---------------------------------------
-- Process to generate stimulus ...
---------------------------------------

   STIMULUS: process
   begin

      -- add stimuli

      wait;
   end process STIMULUS;
 
---------------------------------------
-- Seven Segment Display...
---------------------------------------
   DISP4(DISPLAY_MS_HR, DISPLAY_LS_HR, DISPLAY_MS_MIN, DISPLAY_LS_MIN);

end TEST;

---------------------------------------
-- configuration...
---------------------------------------

configuration CFG_T_DDRV4 of T_DDRV4 is
   for TEST
   end for;
end CFG_T_DDRV4;