t_a_fsm.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_a_fsm.vhd
-- Testbench for the Alarm Controller block (Lab 11)
--
----------------------------------------------------

Library IEEE;
use IEEE.Std_Logic_1164.all; 
use std.textio.all;

use work.P_ALARM_TEST.all;   -- package holds procedures defining commands

entity T_A_FSM is
end T_A_FSM;

architecture TEST of T_A_FSM is

signal CLK                       : std_logic := '0';
signal RESET                     : std_logic := '0';
signal ONE_SEC_PULSE               : std_logic := '0'; 
signal ALARM_BUTTON, TIME_BUTTON : std_logic := '0';
signal KEY                       : std_logic_vector(3 downto 0) := "1010";
signal LOAD_NEW_A, SHOW_A,
       SHOW_NEW_TIME, LOAD_NEW_C : std_logic;
signal SIM_END                   : boolean := FALSE;

   component A_FSM
   port( CLK            : in std_logic;
         RESET          : in std_logic;
         KEY            : in std_logic_vector(3 downto 0);
         ALARM_BUTTON   : in std_logic;
         TIME_BUTTON    : in std_logic;
         ONE_SECOND     : in std_logic;
         LOAD_NEW_A     : out std_logic;
         SHOW_A         : out std_logic;
         SHOW_NEW_TIME  : out std_logic;
         LOAD_NEW_C     : out std_logic);
   end component;

begin 
   -- Generate CLK and Reset waveforms
   CLK <= not CLK after PERIOD/2 when SIM_END = FALSE else '0'; 
   RESET <= '1' after PERIOD, '0' after 3*PERIOD; 

   ONE_SEC_PULSE <= not ONE_SEC_PULSE  after PERIOD when SIM_END = FALSE else '0';

   -- Instantiate the block under test
   CONTROL: A_FSM
   port map( CLK           => CLK,
             RESET         => RESET,
             KEY           => KEY,
             ALARM_BUTTON  => ALARM_BUTTON,
             TIME_BUTTON   => TIME_BUTTON,
             ONE_SECOND    => ONE_SEC_PULSE,
             LOAD_NEW_A    => LOAD_NEW_A,
             SHOW_A        => SHOW_A,
             SHOW_NEW_TIME => SHOW_NEW_TIME,
             LOAD_NEW_C    => LOAD_NEW_C);

------------------------------------------------------------------------
-- COMMAND INPUT process
-- This process reads command strings from  the test file "command.txt"
-- and generates input stimulus to the block under test, depending upon
-- which command is read in. The commands are:
--
-- SETAL DDDD -- set alarm <time> 
-- SETTI DDDD -- set time  <time>
-- SHWAL      -- show alarm
-- COUNT D    -- advance the clock by <clock_cycles>
-- KTOUT      -- test the keypad timeout
--
-- (D = integer ascii character in range 0-9)
------------------------------------------------------------------------
   COMMAND_INPUT: process 
      file COMFILE                   : text is in "command.txt";
      variable L                     : line;
      variable CMD                   : string(1 to 5);
      variable SETTING               : string(1 to 4);
      variable CYCLES, SEPARATOR     : character;
   begin
      -- if there are still lines to read in the text file ...
      while not ENDFILE(COMFILE) loop

         -- read in next line from text file, then read the first text string
         -- from the line and call this CMD.
         readline(COMFILE, L);
         read (L, CMD);

         -- Depending on what the command is, read in any extra information
         -- from the line read from the file and then call the appropriate
         -- command procedure
         case CMD is
            when "SHALM" =>  -- read any extra information you require
                             -- then call the appropriate command procedure;
            when "SETAL" => read (L, SEPARATOR);
                            read (L, SETTING);
                            DO_SETAL(SETTING, KEY, ALARM_BUTTON);
            when "SETTI" =>  -- read any extra information you require
                            -- then call the appropriate command procedure;
            when "COUNT" => read(L, SEPARATOR);
                            read(L, CYCLES);
                            DO_COUNT(CYCLES);
            when "KTOUT" =>  -- read any extra information you require
                            -- then call the appropriate command procedure;
            when others => assert FALSE report "Unrecognised Instruction"
                              severity FAILURE;
         end case;

      end loop;

      -- No new lines to read from file, so report simulation complete and
      -- stop clock generator with SIM_END signal
      assert FALSE report "Simulation complete" severity NOTE;
      SIM_END <= TRUE;

      wait;

   end process COMMAND_INPUT;

------------------------------------------------------------------------
-- COMMAND INPUT process
-- This process reads command strings from  the test file "command.txt"
-- and generates input stimulus to the block under test, depending upon
-- which command is read in
------------------------------------------------------------------------
   TRACE_OUTPUT: process 
      file TRACEFILE          : text is out "trace.txt";
      variable L              : line;
      variable CTRL_OUTPUTS   : std_logic_vector(1 to 4);

    begin
        wait until CLK'event and CLK = '1';

       -- Build up the line to be written out:
       -- first print current simulation time, then a space,...
        write(L, NOW);
        write(L, ' ');

       -- ... then type-convert the state-machine outputs and add them
       -- to the line to be written.
        CTRL_OUTPUTS := (LOAD_NEW_A & SHOW_A & SHOW_NEW_TIME & LOAD_NEW_C);
        for I in CTRL_OUTPUTS'range loop
            write(L, STDU2CHAR(CTRL_OUTPUTS(I)));
        end loop;

        -- write out the line you have built-up to the output file
        writeline(TRACEFILE, L);        

    end process TRACE_OUTPUT;

end TEST;                


configuration CFG_T_A_FSM of T_A_FSM is
for TEST
end for;
end CFG_T_A_FSM;