t_timeg.vhd

Workshop vhdl code from Esperan

-----------------------------------------------------------------------
-- 
-- Original Code Copyright (c) 1999 by Esperan. All rights reserved.
-- www.esperan.com
-- 
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice. 
--
-- Esperan VHDL Alarm Clock Lab Exercise Design V5.0
--
-- T_timegen.vhd
-- Test bench for the Alarm Clock Timing Generator
--
--------------------------------------------------------------- 

                               -- WHAT LIBRARY?
use IEEE.Std_Logic_1164.all; 

                               -- SPECIFY THE ENTITY
architecture TEST of T_TIMEG is

   component TIMEGEN
   port( CLK             : in std_logic;
         RESET           : in std_logic;
         STOPWATCH       : in std_logic;
         ONE_SECOND      : out std_logic;
         ONE_MINUTE      : out std_logic);
   end component;

   signal ONE_SECOND, ONE_MINUTE  : std_logic;
   signal STOPWATCH, RESET        : std_logic;
   signal CLK                     : std_logic;   -- ANY INITIAL VALUE NEEDED?

   constant PERIOD     : time := 10 ns;

begin

   ---------------------------------------------
   -- instantiate UUT
   ---------------------------------------------

   uut:  TIMEGEN port map ();  -- COMPLETE THE PORT MAP

   ---------------------------------------------
   -- infinite clock generator 
   ---------------------------------------------

   CLK <=  ????? after PERIOD/2;                         -- COMPLETE CLOCK GENERATOR

   --------------------------------------------------
   -- Stimulus: 
   -------------------------------------------------
   STIMULUS : process
   begin


                                                   -- PUT YOUR STIMULUS HERE

   end process STIMULUS;

end TEST;

configuration CFG_T_TIMEG of T_TIMEG is
   for TEST
   end for;
end CFG_T_TIMEG;