t142.vhd

Workshop vhdl code from Esperan

entity TEST is
	port( 	A : in  bit_vector(15 downto 0);
		Z : out bit_vector(7 downto 0));
end TEST;
architecture T142 of TEST is
	signal TMP_A : bit_vector(15 downto 0);
	alias SIGN is TMP(15);
	alias HIGH_A is TMP_A(15 downto 8);
begin
	TMP_A <= A;
	Z <= not HIGH_A;
end T142;