t52.vhd

Workshop vhdl code from Esperan

--
-- This file tests support for Next, Exit Statements inside a while loop.
--
entity TEST is
	port (A : in  bit_vector (7 downto 0);
	      B : in  bit;
	      Z : out bit_vector (7 downto 0));
end TEST;
architecture T52 of TEST is
begin
	process(B, A)
		variable I : integer;
	begin
		I:= -1;
		while true loop
			I := I + 1;
			exit when (I > 7);
			if (A(I) = '0') then
				Z(I) <= '0';
				next;
			end if;
			Z(I) <= B;
		end loop;
	end process;
end T52;