t41.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 41 行

--
-- This file tests support for Support of the 'when others' to infer safe state machines (with user defined types).
-- If your synthesis tool supports safe state encoding, the gate level simulation of this design should set the state
-- machine state to ST0 or "00" if the value of the state variable is set to "11" at power up.
--
entity TEST is
	port ( 	A,B,CLK,RESET : in  bit;
       		Z             : out bit);
end TEST;
architecture T41 of TEST is
	type T_STATE is (ST0, ST1, ST2);
	signal STATE : T_STATE;
begin
	process (CLK, RESET)
	begin
		if RESET = '1' then
			STATE <= ST0;
			Z <= '0';
		elsif (CLK'event and CLK='1') then
			case STATE is 
				when ST0 =>
					Z <= '0';
					if A='1' then
						STATE <= ST1;
					end if;
				when ST1 => 
					Z <= '1';
					if B='1' then 
						STATE <= ST2;
					end if;
				when ST2 => 
					STATE <= ST0;
				when others =>
					STATE <= ST0;
			end case;
		end if;
	end process;
end T41;