t111.vhd

Workshop vhdl code from Esperan

--
-- This file tests for tri-state inference with the 'Z' assignment.
--
library IEEE;
use IEEE.STD_Logic_1164.all;
entity TEST is
	port( A,EN_A : in std_logic;
	      Q : out std_logic);
end TEST;

architecture T111 of TEST is
begin
	process(A, EN_A)
	begin
		if EN_A = '1' then
			Q <= A;
		else
		  	Q <= 'Z';
		end if;
	end process;
end T111;