t152.vhd

Workshop vhdl code from Esperan

--
-- This file implements Latch inference on signals in a combinational process 
-- using incomplete sensitivity list. The signal Z should be allocated a latch 
-- if the synthesis tool allows you the use of incomplete sensitivity list.
-- Failing that you should either get a warning or an error message.
-- 
entity TEST is 
	port( A,B,SEL : in bit;
	      Z : out bit);
end TEST;
architecture T152 of TEST is
begin
	process(A,B)
	begin
		if SEL='1' then
			Z <= A;
		else
			Z <= B;
		end if;
	end process;
end T152;