t161.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 30 行

--
-- This file tests support for multiple wait statements inside a process.
--
entity TEST is
	port( CLK, RESET : in bit;
	      RD, WR     : out bit);
end TEST;
architecture T161 of TEST is
begin
	process
	begin
		RESET_LOOP: loop
			if RESET ='1' then
				RD <= '0';
				WR <= '0';
			end if;
			wait until CLK='1' and CLK'event;
			next RESET_LOOP when reset = '1';
			RD <= '1';
			wait until CLK='1' and CLK'event;
			next RESET_LOOP when reset = '1';
			RD <= '0';
			WR <= '1';
			wait until CLK='1' and CLK'event;
			next RESET_LOOP when reset = '1';
		end loop RESET_LOOP;
	end process;
end T161;