index.txt

Workshop vhdl code from Esperan

Synthesis Tools Language Support.

1. Arrays 
	1.1  Array of arrays (two dimensions).
	1.2  Array of arrays (more than two dimensions).
	1.3  Arrays with user defined types as index.
	1.4  Multi-dimensional arrays (two dimensions).
	1.5  Multi-dimensional arrays (more than two dimensions).
	1.6  Array types on ports (arrays of integers).
	1.7  Array types on ports (arrays of vectors).
	1.8  Use of aggregate with arrays.
	1.9  Use of concatenation with arrays.

2.  Records
  	2.1 Records of simple types.
	2.2 Records of records.
	2.3 Records of arrays.
	2.4 Record types on ports.
	2.5 Use of aggregates with records.

3.  Generics
	3.1  Generic map with integers.
	3.2  Generic map with vectors.
	3.3  Top level generics.

4.  Case Statement
	4.1  Support of the 'when others' to infer safe state machines (with user defined types).
	4.2  Use of the don't care '----' to perform optimisation.

5.  While Loop Statement
	5.1  While condition evaluated as a constant.
	5.2  Next, Exit Statements.

6.  For Loop Statement
	6.1  Next, Exit Statements.

7.  Generate Statement
	7.1  'if generate' statement used with generics.

8.  Attributes
	8.1 Pre-defined attributes.
	8.2 User defined attributes.

9.  Blocks and Guarded Blocks
	9.1  Simple block statement.
	/ 9.2  Guarded block statement. /
	/ 9.3  Port map and Generic map in block statements. /

10.  User Defined Sub-Programs
	10.1  Support for user defined functions.
	10.2  Support for user defined procedures.
	/ 10.3  Synthesis of user defined resolution functions. /

11.   Tri-State Inference
	11.1  The 'Z' assignment.
	/ 11.2  Use of guarded blocks. /
	/ 11.3  Use of disconnected assignment. / 

12.   Component Instantiation 
	12.1  Support for component instantiation inside a generate statement.
	12.2  Support for the generic map construct.
	12.3  Component binding and configuration using default binding.
	12.4  Component binding and configuration using architecture configuration.
	/ 12.5  Component binding and configuration using top level configuration. /
	/ 12.6  Component binding and configuration using referencing configuration. /
	12.7  Support for the VHDL'93 direct instantiation.

13.  User Defined Packages
	13.1  Separate files for the package header and the package body.
	13.2  Support for subprograms in packages.
	13.3  Support for differed constants.
	13.4  Component declaration in packages.

14.   Aliases
	14.1  Signals Alias.
	14.2  Support for the VHDL'93 alias style.

15.   Processes and Register/Latch Inference.
	15.1  Latch inference on signals in a combinational process using incomplete assignment.
	15.2  Latch inference on signals in a combinational process using incomplete sensitivity list.
	15.3  Latch inference on variables in a combinational process.
	15.4  Register inference on signals in clocked processes.
	15.5  Register inference on variables in clock processes.
	15.6  Use of the function call rising_edge() for edge detection.
	15.7  Support for ' if clk='1' ' for edge detection.
	15.8  Support for ' wait until clk='1' ' for edge detection.  
	15.9  Use of the attribute 'not stable for edge detection.

16.   Wait Statement
	16.1 Support for multiple wait statements inside a process.

17.   Resource Sharing
	17.1  Optimisation of concurrent expressions.
	17.2  Mutually exclusive expressions.
	17.3  Mutually exclusive function calls.
	17.4  Exclusive expressions outside the same if statement.
	17.5  Use of identical expressions more than once inside the same process.

18.   Ranged Integers
	18.1  Arithmetic expressions on positive ranged integers.
	18.2  Arithmetic expressions on negative ranged integers.

19.   Resource Sharing for speed 
	19.1  Slow parity generator structure example.
	19.2  Faster parity generator structure example.
	19.3  Slow barrel shifter example.
	19.4  Faster barrel shifter example.