t158.vhd

Workshop vhdl code from Esperan

--
-- This file tests Support for ' wait until clk='1' ' for edge detection.  
--
entity TEST is 
	port( D, CLK : in bit;
	      Q : out bit);
end TEST;
architecture T158 of TEST is
begin
	process
	begin
		wait until CLK='1';
		Q <= D;
	end process;
end T158;