t61.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 25 行

--
-- This file tests support for Next, Exit Statements inside for loops.
--
entity TEST is
	port (A : in  bit_vector (7 downto 0);
	      B : in  bit;
	      Z : out bit_vector (7 downto 0));
end TEST;
architecture T61 of TEST is
begin
	process(B, A)
	begin
		Z <= "11111111";
		for I in 0 to 7 loop
			exit when (A = "10101010");
			if (A(I) = '0') then
				Z(I) <= '0';
				next;
			end if;
			Z(I) <= B;
		end loop;
	end process;
end T61;