t182.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 15 行

--
-- This file tests the implementation of ranged integer (negative).
-- This code should infer the use of a 4 bits for the signals 
-- A and B (3 for the max value, 1 for the sign). Y will be 5 bits (4 for the
-- max value, 1 for the sign bit). 
--
entity TEST is 
	port( A,B : in integer range -3 to 7;
	      Y   : out integer range -6 to 14);
end TEST;
architecture T182 of TEST is
begin
	Y <= A + B;
end T182;