t151.vhd

Workshop vhdl code from Esperan

--
-- This file implements Latch inference on signals in a combinational
-- process using incomplete assignment. The synthesis report should account for one latch.
--

entity TEST is 
	port( D, EN : in bit;
	      Q : out bit);
end TEST;
architecture T151 of TEST is
begin
	process(D, EN)
	begin
		if EN='1' then
			Q <= D;
		end if;
	end process;
end T151;