t122.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 30 行

--
-- This file tests the support for the generic map construct.
-- 
entity AND_GATE is
	generic (SIZE : integer);
	port( A, B : in bit_vector(SIZE-1 downto 0);
	      Z : out bit_vector(SIZE-1 downto 0));
end AND_GATE;
architecture RTL of AND_GATE is
begin
	Z <= A and B;
end RTL;

entity TEST is
 	port(	A,B : in bit_vector(4 downto 0);
		Z : out bit_vector(4 downto 0));
end TEST;
architecture T122 of TEST is
	component AND_GATE 
		generic (SIZE : integer);
		port( A, B : in bit_vector(SIZE-1 downto 0);
	      	      Z : out bit_vector(SIZE-1 downto 0));
	end component;
begin
	U1: AND_GATE
		generic map (SIZE => 5)
		port map (A, B, Z);
end T122;