t157.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 17 行

--
-- This file tests Support for ' if clk='1' ' for edge detection.
--
entity TEST is 
	port( D, CLK : in bit;
	      Q : out bit);
end TEST;
architecture T157 of TEST is
begin
	process(CLK)
	begin
		if (CLK='1') then
			Q <= D;
		end if;
	end process;
end T157;