t82.vhd

Workshop vhdl code from Esperan

--
-- This file tests support for Simple block statement.
--
entity TEST is 
	port( A : in  bit_vector(0 to 4);
	      Z : out bit);
end TEST;

architecture T82 of TEST is
	signal TMP_A: bit_vector(0 to 4);
	attribute MIDDLE_BIT : integer;
	attribute MIDDLE_BIT of TMP_A: signal is 2;
begin
	TMP_A <= A;
	Z <= TMP_A(TMP_A'MIDDLE_BIT);
end T82;