t33.vhd

Workshop vhdl code from Esperan

--
-- This file tests support for Top level generics. Your synthesis tool
-- should allow you to set up the value for the generic SIZE prior synthesis.
--
entity TEST is
	generic (SIZE : integer);
	port( 	A,B : in  bit_vector(SIZE -1 downto 0);
		Z   : out bit_vector(SIZE -1 downto 0));
end TEST;
architecture RTL of TEST is
begin
	Z <= A and B;
end RTL;