t192.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 27 行

--
-- This example represents a 64 bit parity generator. The following code
-- implies a 32 * (xor time unit) + 1 delay due to its structure based on a double
-- for loop. The test case t191.vhd illustrates how the same design written differently 
-- will increase the critical path by almost twice the value of this design's.
--
entity TEST is
	port( A : in  bit_vector(63 downto 0);
	      Z : out bit);
end TEST;
architecture T192 of TEST is
begin
	process(A)
		variable TMP: bit_vector(1 downto 0);
	begin
		TMP := (others => '0');
		for I in 0 to 31 loop
			TMP(0) := TMP(0) xor A(I);
		end loop;
		TMP(1) := A(32);
		for I in 33 to 63 loop
			TMP(1) := TMP(1) xor A(I);
		end loop;
		Z <= TMP(0) xor TMP(1);
	end process;
end T192;