t17.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 19 行

--
-- This file tests support for Array types on ports (arrays of vectors).
-- This test assumes that user defined packages are supported by your
-- synthesis tool.
--
package P_TEST is
	type VECT_ARRAY is array (0 to 7) of bit_vector(3 downto 0);
end P_TEST;

use WORK.P_TEST.all;
entity TEST is
	port(	A_IN : in  VECT_ARRAY;
		B_OUT: out VECT_ARRAY);
end TEST;
architecture t17 of TEST is
begin
	B_OUT <= A_IN;
end t17;