t121.vhd

Workshop vhdl code from Esperan

--
-- This file tests support component instantiation inside a generate statement.
--
entity HALFADD is
	port( A, B : in bit;
	      SUM, CARRY : out bit);
end HALFADD;
architecture RTL of HALFADD is
begin
	SUM <= A xor B;
	CARRY <= A and B;
end RTL;

entity TEST is
 	port(	A,B : in bit_vector(0 to 4);
		SUM, CARRY : out bit_vector(0 to 4));
end TEST;
architecture T121 of TEST is
	component HALFADD 
		port( A, B : in bit;
	      	      SUM, CARRY : out bit);
	end component;
begin
	GEN_5_HALFADD: for I in 0 to 4 generate
		HALFADD_5: HALFADD
			port map(A(I), B(I), SUM(I), CARRY(I));
	end generate;
end T121;