t31.vhd

Workshop vhdl code from Esperan

--
-- This file tests support for Generic map with integers.
--
entity AND_GATE is
	generic (SIZE : integer);
	port( 	A,B : in  bit_vector(SIZE -1 downto 0);
		Z   : out bit_vector(SIZE -1 downto 0));
end AND_GATE;
architecture RTL of AND_GATE is
begin
	Z <= A and B;
end RTL;

entity TEST is
	port( 	A,B : in  bit_vector(3 downto 0);
	    	Z   : out bit_vector(3 downto 0));
end TEST;
architecture T31 of TEST is
	component AND_GATE
		generic (SIZE : integer);
		port( 	A,B : in  bit_vector(SIZE -1 downto 0);
			Z   : out bit_vector(SIZE -1 downto 0));
	end component;
begin
	U1: AND_GATE 
		generic map (SIZE => 4)
		port map (A,B,Z);
end T31;