t42.vhd

Workshop vhdl code from Esperan

--
-- This file tests support for the use of the don't care "----" to perform optimisation.
-- This notation should indicate to your synthesis tool to optimize the logic for the remaining
-- cases of the decoder.
--
library IEEE;
use IEEE.Std_Logic_1164.all;
entity TEST is
	port (	A : in  std_logic_vector(2 downto 0);
		Z : out std_logic_vector(7 downto 0));
end TEST;
architecture T42 of TEST is
begin
	process(A)
	begin
		case A is
			when "000" =>
				 Z <= "11110000";
			when "001" =>
				 Z <= "00001111";
			when "010" =>
				 Z <= "00110011";
			when "100" =>
			         Z <= "11001100";
			when others => 
			 	 Z <= "--------";
		end case;
	end process;
end T42;