t134.vhd

Workshop vhdl code from Esperan

--
-- This file tests support for Component declaration in packages.
--
entity AND_GATE is
	port( A, B : in bit_vector(4 downto 0);
	      Z : out bit_vector(4 downto 0));
end AND_GATE;
architecture RTL of AND_GATE is
begin
	Z <= A and B;
end RTL;

package P_TEST is
	component AND_GATE 
		port( A, B : in bit_vector(4 downto 0);
	      	      Z : out bit_vector(4 downto 0));
	end component;
end P_TEST;

use WORK.P_TEST.all;
entity TEST is
 	port(	A,B : in bit_vector(4 downto 0);
		Z : out bit_vector(4 downto 0));
end TEST;
architecture T123 of TEST is
begin
	U1: AND_GATE port map (A, B, Z);
end T123;