t91.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 28 行

entity TEST is 
	port( A : in  bit_vector(0 to 3);
	      Z : out bit);
end TEST;

architecture T91 of TEST is
begin
	blk_1: block
		signal TMP_A : bit_vector(0 to 3);
		constant VAL : bit_vector(0 to 3) := "1101";
	begin
		TMP_A <= A;
		process (TMP_A)
			variable TMP : bit;
		begin
			TMP:= '0';
			if TMP_A < VAL then
				for I in TMP_A'range loop
					TMP:=TMP xor TMP_A(I);
				end loop;
				Z <= TMP;
			else
				Z <= '0';
			end if;	
		end process;
	end block blk_1;
end T91;