t153.vhd

Workshop vhdl code from Esperan

--
-- This file implements Latch inference on variables in a combinational
-- process. The variable TMP is read before assigned a value to. Hence 
-- implying a latch memory element. 
--
entity TEST is 
	port( A, RST : in bit;
	      Z : out bit);
end TEST;
architecture T153 of TEST is
begin
	process(A, RST)
		variable TMP : bit;
	begin
		if RST = '1' then
			TMP := '0';
		else
			Z <= not TMP;
			TMP := A;
		end if;
	end process;
end T153;