t71.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 29 行

--
-- This  file tests support for the 'if generate' statement used with generics.
--
library IEEE;
use IEEE.Std_Logic_1164.all;
entity TEST is
	generic(REGISTERED : boolean);
	port (	A,B : in  std_logic;
		Z   : out std_logic);
end TEST;
architecture T71 of TEST is
begin
	TRUE_CONDITION: if REGISTERED generate
		process (B)	
		begin
			if B'event and B='1' then
				Z <= not A;
			end if;
		end process;
	end generate TRUE_CONDITION;

	FALSE_CONDITION: if not REGISTERED generate
		process (A)
		begin
			Z <= not A;
		end process;
	end generate FALSE_CONDITION;
end T71;