t123.vhd

Workshop vhdl code from Esperan

--
-- This file tests the support for Component binding and configuration using default binding.
-- 
entity AND_GATE is
	port( A, B : in bit_vector(4 downto 0);
	      Z : out bit_vector(4 downto 0));
end AND_GATE;
architecture RTL of AND_GATE is
begin
	Z <= A and B;
end RTL;

entity TEST is
 	port(	A,B : in bit_vector(4 downto 0);
		Z : out bit_vector(4 downto 0));
end TEST;
architecture T123 of TEST is
	component AND_GATE 
		port( A, B : in bit_vector(4 downto 0);
	      	      Z : out bit_vector(4 downto 0));
	end component;
begin
	U1: AND_GATE port map (A, B, Z);
end T123;

configuration CFG_TEST of TEST is
	for T123
	end for;
end CFG_TEST;