t181.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 13 行

--
-- This file tests the implementation of ranged integer (positive).
-- This code should infer the use of a 3 bits adder.
--
entity TEST is 
	port( A,B : in integer range 0 to 7;
	      Y   : out integer range 0 to 15);
end TEST;
architecture T181 of TEST is
begin
	Y <= A + B;
end T181;