t24.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 25 行

--
-- This file tests support for Record types on ports. This test assumes that
-- user defined packages are supported by your synthesis tool.
-- 
package P_TEST is
	type T_DATA is record 
		PARITY 	: bit;
		DATA 	: bit_vector(3 downto 0);
		ADDRESS : integer range 0 to 7;
	end record;
end P_TEST;

use WORK.P_TEST.all;
entity TEST is
	port( A	: in  T_DATA;
	      Z : out T_DATA);
end TEST;
architecture T24 of TEST is
	signal RX_DATA : T_DATA;
begin
	RX_DATA <= A;
	Z <= RX_DATA;
end T24;