t127.vhd

Workshop vhdl code from Esperan

--
-- This file tests support for the VHDL'93 direct instantiation.
--
entity AND_GATE is
	port( A, B : in bit_vector(4 downto 0);
	      Z : out bit_vector(4 downto 0));
end AND_GATE;
architecture RTL of AND_GATE is
begin
	Z <= A and B;
end RTL;

entity TEST is
 	port(	A,B : in bit_vector(4 downto 0);
		Z : out bit_vector(4 downto 0));
end TEST;
architecture T127 of TEST is
begin
	U1: entity WORK.AND_GATE(RTL) port map (A, B, Z);
end T127;