t18.vhd

来自「Workshop vhdl code from Esperan」· VHDL 代码 · 共 19 行

--
-- This file tests the support for the use of aggregate with arrays.
--
entity TEST is
	port (	A : in  bit_vector(3 downto 0);
		Z : out bit_vector(3 downto 0));
end TEST;
architecture T18 of TEST is 
	subtype NIBBLE is bit_vector(3 downto 0);
	type T_A_OF_A is array (0 to 7) of NIBBLE; 
	signal MY_ARRAY_A, MY_ARRAY_B : T_A_OF_A;
begin 
	MY_ARRAY_A <= (7 => MY_ARRAY_B(0), 6 => A, others => "0000");
	MY_ARRAY_B <= (others => (others => '1'));
	Z <= MY_ARRAY_A(6);
end T18;