timer.vhd.bak

用VHDL实现的完整数字钟代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FM IS
PORT(CLK1024,CLK2048:IN STD_LOGIC;
       FS10: IN STD_LOGIC_VECTOR(3 DOWNTO 0);----miao shiwei
      
       FS1:  IN STD_LOGIC_VECTOR(3 DOWNTO 0);----miao gewei
       FM10:  IN STD_LOGIC_VECTOR(3 DOWNTO 0);--- minnute 10wei
       FM1:  IN STD_LOGIC_VECTOR(3 DOWNTO 0);----minute ge wei
       QFM:  OUT STD_LOGIC);-----------------------输出
END FM;
ARCHITECTURE one OF FM IS
BEGIN
PROCESS( FS10, FS1, FM10,FM1,CLK1024,CLK2048)    
VARIABLE FSI1,FSI10,FMI1,FMI10:  STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE CLKI1024,CLKI2048: STD_LOGIC;
BEGIN
 FMI10:=FM10;FMI1:=FM1;FSI10:=FS10;FSI1:=FS1;
 CLKI1024:=CLK1024;CLKI2048:=CLK2048;
 IF FMI10=5 AND FMI1=9 AND FSI10=5 AND(FSI1="0001" OR FSI1=3 OR FSI1=5 OR FSI1=7) THEN 
   QFM<=CLKI1024;---------59分51、53、55、57秒1024HZ信号输出
 ELSIF FMI10=5 AND FMI1=9 AND FSI10=5 AND FSI1=9 THEN 
   QFM<=CLKI2048;---------------59分59秒2048HZ信号输出
 END IF;
END PROCeSS;
END ;